The physical verification process for an integrated circuit (IC) is a design step taken by semiconductor manufacturers before commencing the fabrication of an IC. Semiconductor foundries define a set of design rules for manufacturing (DRM) for IC designers to follow in order to ensure successful manufacture and high yield of a design during the fabrication process. The DRM are defined as a set of geometric relationships between manufacturing layers, layers which in turn are used to create an IC. A physical design layout can include hundreds of layers used during the fabrication process to create transistors and electrical interconnect in the IC. The semiconductor process has grown in complexity and a physical design layout has to adhere to thousands of design rules before a design can be successfully fabricated. Use of a design rule checking (DRC) physical verification tool is an industry standard process for implementing the semiconductor's DRM.
The DRM can define many different parameters, such as width, spacing, angle, enclosure, density and electrical connectivity rules for design layers, which in turn are translated into a DRC runset. A DRC runset is defined as set of DRC operations that verify the required DRM rules. A DRC tool provides a set of operations, or commands, which a designer uses to build a sequence of DRC commands to satisfy each DRM rule. DRM rules commonly result in a DRC runset with 20,000 or more DRC commands for technology nodes smaller than 28 nanometers (nm). Modern DRC physical verification tools have a large suite of geometric and electrical commands to effectively implement the complex DRM rules. Many of these geometric and electrical commands result in the implementation of a unique algorithm that is not shared between individual commands, thus resulting in a very complex DRC tool with many algorithms.
Large ICs are typically built using a hierarchical method that begins with the creation of small child cells which are combined into larger parent cells, which then are successively used to build larger and larger cells to create an IC hierarchical design. Physical verification tools take advantage of the hierarchy in a design to efficiently process today's extremely large designs. Various forms of flattening processes are an alternative to hierarchical processing, but those flattening processes can result in very large increases in processing time and are often not feasible for design verification.